Perform RTL/GLS verification tasks mostly in SystemVerilog from project planning to closure throughout the complete digital design cycle. Work closely with team members across the globe. Always strive to improve your own skills to meet 5 Systems quality.
What we offer
- Attractive compensation package (option)
- Flexible working hours and full home office
- Improving your professional skills
- Innovative projects, leading-edge technologies
- Fun at work
What we’d like to see
- Degree in Electrical Engineering or Computer Science is preferred
- Experience with Hardware Description Languages (Verilog, SystemVerilog, VHDL)
- Exposure to ASIC or FPGA design flows
- Familiarity with standard or wide spread protocols (APB, AHB, AXI, SPI, etc.)
- Experience with dynamic verification methodologies
- Experience with scripting languages (Perl, TCL, Python, etc.)
- Proficiency in English (both written and oral)
What’s nice to have
- Experience with static verification
- Exposure to Co-Verification of Hardware and Software
- Vim + Tmux ☺
